1. Field of the Invention
The present invention generally relates to sample hold circuits, and more particular to a sample hold circuit which can reduce a distortion rate of an output waveform thereof.
2. Prior Art
FIG. 1 is a circuit diagram showing an example of a conventional non-inversion type sample hold circuit. In FIG. 1, 1 designates an input terminal supplied with an audio input signal, for example, 2 designates an operational amplifier, 3 designates a switch which is turned on or off by a sampling pulse, 4 designates a capacitor, 5 designates a buffer amplifier having a high input impedance and a gain of one (+1), and 6 designates an output terminal. When the switch 3 is turned on, the capacitor 4 is charged up to the state where the charged level thereof becomes equal to an input signal level. On the other hand, when the switch 3 is turned off, the charged voltage of the capacitor 4 is outputted as a sample voltage via the buffer amplifier 5 and the output terminal 6 in series.
FIG. 2 is a circuit diagram showing an example of a conventional inversion type sample hold circuit. In FIG. 2, 8 designates as input terminal, 9 and 10 designate resistors having the same resistance R, 11 and 12 designate switches which are turned on and off in synchronism with the sampling pulse, 13 designates an integration circuit which is constituted by an amplifier 14 and a capacitor 15, and 16 designates an output terminal. When an input signal S.sub.i such as an audio signal is supplied to the input terminal 8 and the switch 11 is turned off and the switch 12 is turned on, the output signal S.sub.o at the output terminal 16 (which is identical to the output signal of the operational amplifier 14) becomes identical to an inverted input signal. In addition, the capacitor 15 is charged up to the state where the charged level of the capacitor 15 equals the output signal level. Next, when the switch 11 is turned on and the switch 12 is turned off, the charged voltage of the capcitor 15 is continously outputted via the output terminal 16, regardless of the input signal variation. FIG. 3(a) shows waveforms of the input signal S.sub.i (shown by a dotted line) and the output signal S.sub.o (shown by a continuous line), and FIG. 3(b) shows an ON/OFF state of the switch 12. In FIG. 3(b), F designates a follow mode period when the output signal S.sub.o follows up the input signal S.sub.i, and H designates a hold mode period when the voltage held in the capacitor 15 is outputted as the output signal S.sub.o.
Meanwhile, the complementary MOS (CMOS) analog switches which have no current offset as shown in FIG. 4 are used for the switches 3, 11 and 12 in the conventional sample hold circuit shown in FIGS. 1 and 2. However, such analog switches have the following problems (1) to (3).
(1) A relatively high level (e.g., approximately .+-.5 V) is required as an amplitude of a sampling pulse S.sub.p (shown in FIG. 5) for the analog switch.
(2) The withstand voltage of the analog switch is relatively low, hence, it is possible to only use a relatively low level signal (e.g., approximately .+-.10 V) as the input signal S.sub.i.
(3) Since the analog switch has an equivalent capacitance E.sub.c as shown by a dotted line in FIG. 4, the switch portion is shorted at the leading edge and trailing edge portions of the sampling pulse S.sub.p due to the relatively larger (dV/dt) of the leadings and traillings, whereby spikes appear in the output signal S.sub.o as shown in FIG. 5. The spikes of the output signal S.sub.o causes noises. Further, the spikes vary the held charge voltage of the capacitor 15, so that the distortion corresponding to the spikes will be generated.
As described heretofore, the CMOS analog switch has various problems.
On the other hand, the analog switch using a bipolar transistor 18 as shown in FIG. 6 is well known. In such as analog switch, the allowable input voltage depends on a withstand voltage between emitter and collector of the transistor 18. Hence, it is possible to input the relatively high voltage, however, since analog switch has the following problems (1) and (2).
(1) When the switch 19 is turned off, the transistor 18 (the analog switch) is turned on. In this case, the base current of the transistor 18 is varied in response to a voltage at an input terminal IN, and the variation of the base current causes the transistor 18 to generate the distortion in the collector voltage of the transistor 18.
(2) In order to turn the transistor 18 on, a certain voltage between emitter and base of the transistor 18 is required. Hence, the input voltage of the sample hold circuit must be lower than a power source voltage thereof and an utilization efficiency of a power source must be deteriorated.